Implementation of non-pipelined and pipelined Data Encryption Standard (DES) using Xilinx Virtex-6 FPGA technology

Taherkhani S., EVER E., Gemikonakli O.

10th IEEE International Conference on Computer and Information Technology, CIT-2010, 7th IEEE International Conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010, Bradford, England, 29 June - 01 July 2010, pp.1257-1262, (Full Text) identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/cit.2010.227
  • City: Bradford
  • Country: England
  • Page Numbers: pp.1257-1262
  • Keywords: Data Encryption Standard, Field Programmable Gate Arrays, Finite state machine, Very High Speed Integrated Circuit Hardware Description Language
  • Middle East Technical University Northern Cyprus Campus Affiliated: Yes

Abstract

Data encryption process can easily be quite complicated and usually requires significant computation time and power despite significant simplifications. This paper discusses about pipelined and non-pipelined implementation of one of the most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation, Virtex-6 Field Programmable Gate Array technology. Finite state machine is used only in non-pipelined implementation, and it is not implemented for the pipelined approach. The testing of the implemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. When pipelined approach is employed on the other hand, 17 clock signals are required for the initial phase only, and one clock signal is sufficient afterwards for each data generation cycle. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to program the design. © 2010 IEEE.