Akademik Veri Yönetim Sistemi
Tezin Türü: Yüksek Lisans
Tezin Yürütüldüğü Kurum: Middlesex University, School of Engineering and Information Sciences, Computer Communications , İngiltere
Tezin Onay Tarihi: 2011
Tezin Dili: İngilizce
Öğrenci: Saeid Taherkhani
Danışman: Enver Ever
Özet:
Data Encryption Standard (DES) and Advanced
Encryption Standard (AES) are two symmetric cryptographic algorithms. These
methods scramble the plaintext or message in a way that it can only be
understood by parties involved in communication. In these techniques, there is
only one key to encrypt or decrypt the message called as shared key or single
key. Sender, in one side, encrypt the message by shared key and in the other
side of communication, once receiver receive the cipher message, it uses shared
key to decrypt the scrambled message to get the original plaintext.
DES and AES are different in the message and key
size that they support and also in the technique to generate the cipher text.
In this thesis, we simulate the algorithms by using a Hardware Description
Language (HDL) in order to compare them in terms of speed and area that they
occupy in a specific programmable hardware chip. A development tool for this
purpose is a software package from XILINX Company, called ISE Design Suite,
system edition. ISE is used to program, simulate, implement and evaluate both
algorithms. The program code is written by Very High Speed Integrated Circuit
Hardware Description Language (VHDL).
Results obtained by simulation of both algorithms in same FPGA chip show
that AES occupy more area than DES. The operating clock frequency of AES design
is 50.24% less than DES design. Results also indicate that throughput of AES
design is 113.3% more than DES design. The main reasons behind the results are,
firstly AES uses 128 bits data while DES is based on 64 bits data and secondly
AES has more complex algorithm and more and larger look-up tables than DES
algorithm.
There are some techniques that improve
the theoretical part of DES such as [14] and others speed up the DES designed
chip based on the different implementation approaches such as [15], [16]. The
last fastest and fully pipelined implementation of DES was declared by Xilinx
Company in [16] where the modification is applied on the implementation part
and not on the theoretical part of DES algorithm. The Throughput of this design
is 15.1 Gbps using VirtexII FPGA platform. In current project the standard
definition of DES is used. Using novel approach in current project in the key
scheduler part of DES makes design faster with the throughput up to 18.82 Gbps
by using Virtex 6 FPGA technology.
Similarly in AES implementation,
there are different approaches to implement S-BOX such as [17], [18], [19], [20], [21]. In Look-up
table implementation of S-BOX, memory is used to keep the LUTs. This block RAM memory
has a constant fetch cycle with duration of 1 clock cycle. In the other hand,
dynamic implementation of S-BOX, the data can be dynamically generated and
there is no need to use constant amount of memory to keep the LUT data. Although,
in order to read the data 4 clock cycles are needed. So there is a trade-off
between memory area and delay in these two approaches. In current project, LUTs
are implemented by the first approach, keeping some area in FPGA only for LUTs.
So the delay due to the dynamic implementation is not applicable here, although
we assign some area for LUT and we can’t utilize this area. The throughput of current AES is 10.24 Gbps which
is significantly more than the design in [17] as one of fast AES implementation.